The invention relates to a microprocessor system for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system. At least part of the full memory on the first bus is additionally backed up by means of another test data store (5) and test data on the first bus. The invention also relates to the microprocessor systems use in motor vehicle controllers.
DE 195 29 434 A1 (P 7959) discloses a microprocessor system for safety-critical applications for controlling or regulating at least partly safety-critical processes, comprising two central processing units (1, 2) integrated in a chip housing, a first and a second bus system, at least one full memory (7) on the first bus system, at least one test data store (51) on the second bus system, which has a reduced store coverage compared to the full memory on the first bus system and in which test data are stored which are connected to data of the memory (7) on the first bus system, and the bus systems comprise comparison and/or driver components which allow the data interchange and/or comparison of data between the two bus systems, and a hardware test data generator (4) is arranged at least on the second bus system. For reasons of redundancy, this microprocessor system contains two homogeneous microprocessor cores (core redundancy) which execute the same program in clock synchronism and in parallel. The bus systems associated with the microprocessor systems are likewise provided in duplicate, but the memory is not of fully symmetrical design, for reasons of cost. It has been found that a high error recognition rate can be achieved if one of the two bus systems stores only test data in a test data store with relatively low storage capacity, said test data being explicitly associated with the full data in the full memory. So that both cores each have all the data available in redundant form, the full data are continually compared with the test data using hardware generators. The hardware generators can either generate test data or can complement the test data for comparison using the full data (data error correction).
It is an aim of the present invention to specify an alternative two-core microprocessor system which likewise comprises a full memory and a test data store of relatively small size for storing redundancy information which is associated with the original data stored in the full memory, and where the microprocessor system has an increased error recognition rate in comparison with corresponding two-core microprocessor systems.